1. Field of the Invention
Example embodiments of the present invention relate generally to an embedded memory and methods thereof, and more particularly to an embedded memory, a method of repairing the embedded memory and a method of retrieving data from the embedded memory.
2. Description of the Related Art
A plurality of function blocks for controlling a display panel and a memory (e.g., which may be accessible to the plurality function blocks and/or a processor controlling the plurality of function blocks) may be embedded in a display driving integrated circuit (DDI). A conventional display panel may display a quarter video graphic array (QVGA) with a resolution of 640×480 pixels and 16 k colors, or alternatively a video graphic array (VGA) with a resolution of 320×200 pixels and 256 k colors. Memory requirements for QVGA may be larger than that of VGA.
Two types of conventional memory may include static random access memory (SRAM) and dynamic random access memory (DRAM). Generally, SRAM may occupy a larger area, per bit, than DRAM. Conventionally, SRAM may be used as the embedded memory in the DDI. However, because higher storage per area may be achieved with DRAM, DRAM may be used within DDIs to increase storage capacity while maintaining a relatively small size.
In SRAM, row failure may be relatively high, and accordingly a redundancy may be allocated to row blocks. In contrast, in DRAM, column failure may be relatively high, and accordingly a redundancy may be allocated to column blocks. Because the memory may be embedded in a single system, a memory scan may be performed by a scan block to facilitate the examination and repair of defective blocks within the memory. In addition, in order to reduce the power dissipation of the system, the scan block may be arranged over the memory region and directly connected to the memory region.
FIG. 1 is a conceptual diagram illustrating memory including scan blocks, column redundancy blocks, and a column redundancy repair function performed by a conventional memory.
Referring to FIG. 1, on the left side of the arrow, a layout of the memory including scan blocks and a column redundancy block may be shown, and on the right side of the arrow, a redundancy repair process may be shown.
Referring to FIG. 1, the conventional memory may include column selection line regions CSL<0> to CSL<n−1> to which a plurality of column selection signals may be applied, and cell arrays C/A<0> to C/A<n−1> in which data recorded in memory cells may be selected based on the column selection signals. Data selected within the cell arrays C/A<0> to C/A<n−1> may be transferred to corresponding scan blocks SCAN<0> to SCAN<n−1>, respectively. A redundancy cell array RC/A<0> may be arranged in parallel with the cell arrays C/A<0> to C/A<n−1>, and a redundancy column selection line region RCSL<0> may be arranged in parallel with the column selection line regions CSL<0> to CSL<n−1>. The redundancy column selection signals may be applied to the redundancy cell array RC/A<0> through the redundancy column selection line regions CSL<0> to CSL<n−1>.
Referring to FIG. 1, a column selection line region and a plurality of column selection signals passing through the column selection line region may use the same reference label. For example, a first column selection signal and a first column selection line region may use the same reference label CSL<0>.
Referring to FIG. 1, on the right side of the arrow, a redundancy repair may be performed by replacing an entire second cell array C/A<1> with a redundancy cell array RC/A<0> if at least one memory cell in the second cell array C/A<1> is defective. The second cell array C/A<1> may be replaced with the redundancy cell array RC/A<0> by controlling the second column selection signal CSL<1> and the redundancy column selection signal RCSL<0>.
Although not shown in FIG. 1, each output of the serially connected scan blocks may be directly connected to a corresponding peripheral circuit, and the corresponding peripheral circuit may examine the function of the cell array by analyzing received serial data.
Referring to FIG. 1, if a memory cell array and a scan block corresponding to the memory cell are directly connected to each other through a conductive (e.g., metallic) line, in the redundancy cell array RC/A<0>, a corresponding scan block may not be arranged. Therefore, data of the redundancy cell array RC/A<0> may not be read when a scan is performed. In order to reduce this problem, the corresponding scan block may be arranged in the redundancy cell array RC/A<0>. However, because the output data of the scan blocks may be serially transmitted, an additional circuit for correctly inserting information of the replaced cell array and an output of the scan block corresponding to the redundancy cell array into the serially transmitted data may be required to attain correct operation. An additional memory peripheral circuit may also be included. Therefore, a layout or size of the conventional memory may increase, as well as a design and/or fabrication time for the conventional memory.